JPH0486942U - - Google Patents
Info
- Publication number
- JPH0486942U JPH0486942U JP12843490U JP12843490U JPH0486942U JP H0486942 U JPH0486942 U JP H0486942U JP 12843490 U JP12843490 U JP 12843490U JP 12843490 U JP12843490 U JP 12843490U JP H0486942 U JPH0486942 U JP H0486942U
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- computer
- combinational logic
- logic data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Debugging And Monitoring (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12843490U JPH0486942U (en]) | 1990-11-30 | 1990-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12843490U JPH0486942U (en]) | 1990-11-30 | 1990-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0486942U true JPH0486942U (en]) | 1992-07-28 |
Family
ID=31875895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12843490U Pending JPH0486942U (en]) | 1990-11-30 | 1990-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0486942U (en]) |
-
1990
- 1990-11-30 JP JP12843490U patent/JPH0486942U/ja active Pending
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